AutoReg and autocom are tools to speed up your design and verification process
Autoreg automatically generate VHDL, TCL and C-code for the interface between SW and the FPGA from the same source file. This ensures that names, addresses, types and so on are always synchronized. Don’t waste time searching for address mismatch.
Autocom gives you a unique debug interface. Through this debug interface you can configure and monitor your FPGA design independent from the SW environment.
Autoreg and autocom are bundles into 1 SW package. Autocom uses the database and interfaces made by autoreg.
A free evaluation version of the tools is now available for download. To download it you must create an account, login and add your email address. We will send you an evaluation version and a corresponding license file.
The demo version is distributed as a self extracting ZIP-file. Since some firewalls blocks downloading .exe files, it is renamed to .txt. The first thing to do after download is to rename the file to .exe. The exe file must then be extracted/unzipped to the hard disk. AutoReg can be located anywhere, but we recommend using folder C:\autoreg. The user guide is located in …\doc\ folder. We recommend to start reading item 1.2 “How to start”
A demo project is included in the evaluation version. This project is used for the tutorial that is described in the user guide. This demo project can be build at several evaluation boards for Xilinx and Altera FPGAs. Is is also easy to adopt to any other hardware.